Double-gate MOSFETs represent new devices that are candidates for succeeding existing planar MOSFETs. A FinFET is one example of a double-gate structure that includes a channel formed in a vertical fin. As the size of FinFET structures continue to shrink down into the deep sub-micron region, it is desirable to use metal gates, such as FinFET gates to further reduce resistance as well as gate conductance, eliminate polysilicon depletion, and tune work function performance. A FinFET gate can be formed by depositing a metal layer (such as Ni, Ti, Co, Pt, etc.) over an exposed polysilicon gate layer, pre-annealing to provide the required diffusion, removing the unreacted metal, and then annealing the semiconductor structure to form a more stable silicide alloy phase. The deposited metal reacts with the exposed polysilicon gate to transform the poly gate into a silicided gate.
While FinFET gate structures provide the above advantages, they introduce difficulties in the manufacturing control process that need to be overcome. One such difficulty with conventional FinFET fabrication methods is in controlling the thickness uniformity of the exposed polysilicon gate layer. Prior to depositing the metal layer over the exposed polysilicon layer, the polysilicon layer is typically etched back by an etch procedure, such as dry or wet etch to reduce its thickness. This etch process typically produces a poly layer having non-uniform thickness (i.e., dishing profile). This may result in incomplete silicidation or inappropriate silicidation phase of the FinFET gate leading to poor device performance.
For this reason and other reasons that will become apparent upon reading the following detailed description, there is a need for a method to precisely control the thickness of the polysilicon gate layer that avoids the shortcomings associated with conventional methods of forming FinFETs.